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FINAL
AM27C1024
1 Megabit (65 K x 16-Bit) CMOS EPROM
DISTINCTIVE CHARACTERISTICS
s Fast access time -- Speed options as fast as 55 ns s Low power consumption -- 20 A typical CMOS standby current s JEDEC-approved pinout -- 40-Pin DIP/PDIP -- 44-Pin PLCC s Single +5 V power supply s 10% power supply tolerance standard s 100% FlashriteTM programming -- Typical programming time of 8 seconds s Latch-up protected to 100 mA from -1 V to VCC + 1 V s High noise immunity s Versatile features for simple interfacing -- Both CMOS and TTL input/output compatibility -- Two line control functions
GENERAL DESCRIPTION
The AM27C1024 is a 1 Megabit, ultraviolet erasable programmable read-only memory. It is organized as 64 Kwords by 16 bits per word, operates from a single +5 V supply, has a static standby mode, and features fast single address location programming. Products are available in windowed ceramic DIP packages, as well as plastic one time programmable (OTP) PDIP and PLCC packages. Data can be typically accessed in less than 55 ns, allowing high-performance microprocessors to operate without any WAIT states. The device offers separate Output Enable (OE#) and Chip Enable (CE#) controls, thus eliminating bus contention in a multiple bus microprocessor system. AMD's CMOS process technology provides high speed, low power, and high noise immunity. Typical power consumption is only 125 mW in active mode, and 100 W in standby mode. All signals are TTL levels, including programming signals. Bit locations may be programmed singly, in blocks, or at random. The device supports AMD's Flashrite programming algorithm (100 s pulses), resulting in a typical programming time of 8 seconds.
BLOCK DIAGRAM
VCC VSS VPP OE# CE# PGM# Output Enable Chip Enable and Prog Logic Y Decoder A0-A15 Address Inputs Data Outputs DQ0-DQ15
Output Buffers
Y Gating
X Decoder
1,048,576 Bit Cell Matrix
06780J-1
Publication# 06780 Rev: J Amendment/0 Issue Date: May 1998
PRODUCT SELECTOR GUIDE
Family Part Number Speed Options VCC = 5.0 V 5% VCC = 5.0 V 10% -55 -55 55 55 40 -70 70 70 40 -90 90 90 45 -120 120 120 50 -150 150 150 65 -200 200 200 75 250 250 75 AM27C1024 -255
Max Access Time (ns) CE# (E#) Access (ns) OE# (G#) Access (ns)
CONNECTION DIAGRAMS
DIP
VPP CE# (E#) DQ15 DQ14 DQ13 DQ12 DQ11 DQ10 DQ9 DQ8 VSS DQ7 DQ6 DQ5 DQ4 DQ3 DQ2 DQ1 DQ0 OE# (G#) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 VCC DQ13 DQ14 DQ15 PGM# (P#) NC A15 A14 A13 A12 A11 A10 A9 VSS A8 A7 A6 A5 A4 A3 A2 A1 A0
06780J-2
PLCC
DU (Note 2) PGM# (P#)
CE (E)
VCC
A15
6 DQ12 DQ11 DQ10 DQ9 DQ8 VSS NC DQ7 DQ6 DQ5 DQ4 7 8 9 10 11 12 13 14 15 16
5
4
3
2
1 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 A13 A12 A11 A10 A9 VSS NC A8 A7 A6 A5
29 17 18 19 20 21 22 23 24 25 26 27 28 DQ3 DQ2 DQ1 DQ0 OE# (G#) A0 A1 A2 A3 DU (Note 2) A4
A14
06780J-3
VPP
Notes: 1. JEDEC nomenclature is in parenthesis. 2. Don't use (DU) for PLCC.
PIN DESIGNATIONS
A0-A15 CE# (E#) = Address Inputs = Chip Enable Input
LOGIC SYMBOL
16 A0-A15 DQ0-DQ15 CE# (E#) PGM# (P#) OE# (G#)
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DQ0-DQ15 = Data Input/Outputs OE# (G#) PGM# (P#) VCC VPP VSS NC 2 = Output Enable Input = Program Enable Input = VCC Supply Voltage = Program Voltage Input = Ground = No Internal Connection AM27C1024
NC
16
ORDERING INFORMATION UV EPROM Products
AMD standard products are available in several packages and operating ranges. The order number (Valid Combination) is formed by a combination of the following:
AM27C1024
-55
D
C
5
B OPTIONAL PROCESSING Blank = Standard Processing B = Burn-In VOLTAGE TOLERANCE 5 = VCC 5%, 55 ns only See Product Selector Guide and Valid Combinations TEMPERATURE RANGE C = Commercial (0C to +70C) I = Industrial (-40C to +85C) E = Extended (-55C to +125C) PACKAGE TYPE D = 40-Pin Ceramic DIP (CDV040) SPEED OPTION See Product Selector Guide and Valid Combinations
DEVICE NUMBER/DESCRIPTION AM27C1024 1 Megabit (64 K x 16-Bit) CMOS UV EPROM
Valid Combinations Valid Combinations AM27C1024-55 VCC = 5.0 V 5% AM27C1024-55 VCC = 5.0 V 10% AM27C1024-70 AM27C1024-90 AM27C1024-120 AM27C1024-150 AM27C1024-200 AM27C1024-255 VCC = 5.0 V 5% DC, DCB, DI, DIB DC, DCB, DI, DIB, DE, DEB DC, DCB, DI, DIB DC5, DC5B, DI5, DI5B Valid Combinations list configurations planned to be supported in volume for this device. Consult the local AMD sales office to confirm availability of specific valid combinations and to check on newly released combinations.
AM27C1024
3
ORDERING INFORMATION OTP EPROM Products
AMD standard products are available in several packages and operating ranges. The order number (Valid Combination) is formed by a combination of the following:
AM27C1024
-55
J
C
5 OPTIONAL PROCESSING Blank = Standard Processing VOLTAGE TOLERANCE 5 = VCC 5%, 55 ns only See Product Selector Guide and Valid Combinations TEMPERATURE RANGE C = Commercial (0C to +70C) I = Industrial (-40C to +85C) PACKAGE TYPE P = 40-Pin Plastic DIP (PD 040) J = 44-Pin Plastic Leaded Chip Carrier (PL 044) SPEED OPTION See Product Selector Guide and Valid Combinations
DEVICE NUMBER/DESCRIPTION AM27C1024 1 Megabit (64 K x 16-Bit) CMOS OTP EPROM
Valid Combinations Valid Combinations AM27C1024-55 VCC = 5.0 V 5% AM27C1024-55 VCC = 5.0 V 10% AM27C1024-70 AM27C1024-90 AM27C1024-120 AM27C1024-150 AM27C1024-200 AM27C1024-255 VCC = 5.0 V 5% JC, PC, JI, PI PC5, PI5, JC5, JI5 Valid Combinations list configurations planned to be supported in volume for this device. Consult the local AMD sales office to confirm availability of specific valid combinations and to check on newly released combinations.
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AM27C1024
FUNCTIONAL DESCRIPTION Device Erasure
In order to clear all locations of their programmed contents, the device must be exposed to an ultraviolet light source. A dosage of 15 W seconds/cm2 is required to completely erase the device. This dosage can be obtained by exposure to an ultraviolet lamp--wavelength of 2537 A--with intensity of 12,000 W/cm2 for 15 to 20 minutes. The device should be directly under and about one inch from the source, and all filters should be removed from the UV light source prior to erasure. Note that all UV erasable devices will erase with light sources having wavelengths shorter than 4000 A, such as fluorescent light and sunlight. Although the erasure process happens over a much longer time period, exposure to any light source should be prevented for maximum system reliability. Simply cover the package window with an opaque label or substance.
VPP = 12.75 V 0.25 V and PGM# LOW will program that particular device. A high-level CE# input inhibits the other devices from being programmed.
Program Verify
A verification should be performed on the programmed bits to determine that they were correctly programmed. The verify should be performed with OE# and CE# at VIL, PGM# at VIH, and VPP between 12.5 V and 13.0 V.
Autoselect Mode
The autoselect mode provides manufacturer and device identification through identifier codes on DQ0- DQ7. This mode is primarily intended for programming equipment to automatically match a device to be programmed with its corresponding programming algorithm. This mode is functional in the 25C 5C ambient temperature range that is required when programming the device. To activate this mode, the programming equipment must force VH on address line A9. Two identifier bytes may then be sequenced from the device outputs by toggling address line A0 from VIL to VIH (that is, changing the address from 00h to 01h). All other address lines must be held at VIL during the autoselect mode. Byte 0 (A0 = VIL) represents the manufacturer code, and Byte 1 (A0 = VIH), the device identifier code. Both codes have odd parity, with DQ7 as the parity bit.
Device Programming
Upon delivery, or after each erasure, the device has all of its bits in the "ONE", or HIGH state. "ZEROs" are loaded into the device through the programming procedure. The device enters the programming mode when 12.75 V 0.25 V is applied to the VPP pin, and CE# and PGM# are at VIL. For programming, the data to be programmed is applied 16 bits in parallel to the data pins. The flowchar t in the Programming section of the EPROM Products Data Book (Section 5, Figure 5-1) shows AMD's Flashrite algorithm. The Flashrite algorithm reduces programming time by using a 100 s programming pulse and by giving each address only as many pulses to reliably program the data. After each pulse is applied to a given address, the data in that address is verified. If the data does not verify, additional pulses are given until it verifies or the maximum pulses allowed is reached. This process is repeated while sequencing through each address of the device. This part of the algorithm is done at VCC = 6.25 V to assure that each EPROM bit is programmed to a sufficiently high threshold voltage. After the final address is completed, the entire EPROM memory is verified at VCC = VPP = 5.25 V. Please refer to Section 5 of the EPROM Products Data Book for additional programming information and specifications.
Read Mode
To obtain data at the device outputs, Chip Enable (CE#) and Output Enable (OE#) must be driven low. CE# controls the power to the device and is typically used to select the device. OE# enables the device to output data, independent of device selection. Addresses must be stable for at least tACC -tOE. Refer to the Switching Waveforms section for the timing diagram.
Standby Mode
The device enters the CMOS standby mode when CE# is at VCC 0.3 V. Maximum VCC current is reduced to 100 A. The device enters the TTL-standby mode when CE# is at VIH. Maximum VCC current is reduced to 1.0 mA. When in either standby mode, the device places its outputs in a high-impedance state, independent of the OE# input.
Output OR-Tieing
To accommodate multiple memory connections, a two-line control function provides: s Low memory power dissipation, and s Assurance that output bus contention will not occur. CE# should be decoded and used as the primary device-selecting function, while OE# be made a common
Program Inhibit
Programming different data to multiple devices in parallel is easily accomplished. Except for CE#, all like inputs of the devices may be common. A TTL low-level program pulse applied to one device's CE# input with
AM27C1024
5
connection to all devices in the array and connected to the READ line from the system control bus. This assures that all deselected memory devices are in their low-power standby mode and that the output pins are only active when data is desired from a particular memory device.
System Applications
During the switch between active and standby conditions, transient current peaks are produced on the rising and falling edges of Chip Enable. The magnitude of
these transient current peaks is dependent on the output capacitance loading of the device. At a minimum, a 0.1 F ceramic capacitor (high frequency, low inherent inductance) should be used on each device between VCC and VSS to minimize transient effects. In addition, to overcome the voltage drop caused by the inductive effects of the printed circuit board traces on EPROM arrays, a 4.7 F bulk electrolytic capacitor should be used between VCC and VSS for each eight devices. The location of the capacitor should be close to where the power supply is connected to the array.
MODE SELECT TABLE
Mode Read Output Disable Standby (TTL) Standby (CMOS) Program Program Verify Program Inhibit Autoselect (Note 3) Manufacturer Code Device Code CE# VIL X VIH VCC 0.3 V VIL VIL VIH VIL VIL OE# VIL VIH X X X VIL X VIL VIL PGM# X X X X VIL VIH X VIH VIH A0 X X X X X X X VIL VIH A9 X X X X X X X VH VH VPP X X X X VPP VPP VPP X X Outputs DOUT High Z High Z High Z DIN DOUT High Z 01h 8Ch
Notes: 1. VH = 12.0 V 0.5 V. 2. X = Either VIH or VIL. 3. A1-A8 and A10-15 = VIL 4. See DC Programming Characteristics for VPP voltage during programming.
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AM27C1024
ABSOLUTE MAXIMUM RATINGS
Storage Temperature OTP Products. . . . . . . . . . . . . . . . . . -65C to +125C All Other Products . . . . . . . . . . . . . . -65C to +150C Ambient Temperature with Power Applied. . . . . . . . . . . . . . -55C to +125C Voltage with Respect to VSS All pins except A9, VPP, VCC . . -0.6 V to VCC + 0.6 V A9 and VPP (Note 2) . . . . . . . . . . . . . -0.6 V to 13.5 V VCC (Note 1). . . . . . . . . . . . . . . . . . . . . -0.6 V to 7.0 V
OPERATING RANGES
Commercial (C) Devices Ambient Temperature (TA) . . . . . . . . . . .0C to +70C Industrial (I) Devices Ambient Temperature (TA) . . . . . . . . .-40C to +85C Extended (E) Devices Ambient Temperature (TA) . . . . . . . .-55C to +125C Supply Read Voltages VCC for 5% devices . . . . . . . . . . +4.75 V to +5.25 V VCC for 10% devices . . . . . . . . . +4.50 V to +5.50 V
Operating ranges define those limits between which the functionality of the device is guaranteed.
Notes:
1. Minimum DC voltage on input or I/O pins -0.5 V. During voltage transitions, the input may overshoot VSS to -2.0 V for periods of up to 20 ns. Maximum DC voltage on input and I/O pins is VCC + 5 V. During voltage transitions, input and I/O pins may overshoot to VCC + 2.0 V for periods up to 20 ns. 2. Minimum DC input voltage on A9 is -0.5 V. During voltage transitions, A9 and VPP may overshoot VSS to -2.0 V for periods of up to 20 ns. A9 and VPP must not exceed +13.5 V at any time. Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure of the device to absolute maximum ratings for extended periods may affect device reliability.
AM27C1024
7
DC CHARACTERISTICS over operating range (unless otherwise specified)
Parameter Symbol VOH VOL VIH VIL ILI ILO ICC1 Parameter Description Output HIGH Voltage Output LOW Voltage Input HIGH Voltage Input LOW Voltage C/I Devices Input Load Current Output Leakage Current VCC Active Current (Note 2) VIN = 0 V to VCC VOUT = 0 V to VCC CE# = VIL, f = 10 MHz, IOUT = 0 mA CE# = VIH CE# = VCC 0.3 V CE# = OE# = VIL, VPP = VCC C/I Devices E Devices E Devices Test Conditions IOH = -400 A IOL = 2.1 mA 2.0 -0.5 Min 2.4 0.45 VCC + 0.5 +0.8 1.0 A 5.0 5.0 50 mA 60 1.0 100 100 mA A A A Max Unit V V V V
ICC2 ICC3 IPP1
VCC TTL Standby Current VCC CMOS Standby Current VPP Supply Current (Read)
Caution: The device must not be removed from (or inserted into) a socket when VCC or VPP is applied. Notes: 1. VCC must be applied simultaneously or before VPP, and removed simultaneously or after VPP.. 2. ICC1 is tested with OE# = VIH to simulate open outputs. 3. Minimum DC Input Voltage is -0.5 V. During transitions, the inputs may overshoot to -2.0 V for periods less than 20 ns. Maximum DC Voltage on output pins is VCC + 0.5 V, which may overshoot to VCC + 2.0 V for periods less than 20 ns.
40 35 30 25 20 1 2 3 4 5 6 7 Frequency in MHz 8 9 10
40 35 30 25 20 -75 -50 -55
Supply Current in mA
Supply Current in mA
0 25 50 75 100 125 150 Temperature in C
06780J-6
06780J-5
Figure 1.
Typical Supply Current vs. Frequency VCC = 5.5 V, T = 25C
Figure 2. Typical Supply Current vs. Temperature VCC = 5.5 V, f = 10 MHz
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AM27C1024
TEST CONDITIONS
5.0 V
Table 1.
Test Condition Output Load
Test Specifications
-55 All others 1 TTL gate 30 20 0.0-3.0 0.45-2.4 1.5 1.5 0.8, 2.0 0.8, 2.0 100 pF ns V V V Unit
Device Under Test CL 6.2 k
2.7 k
Output Load Capacitance, CL (including jig capacitance) Input Rise and Fall Times Input Pulse Levels
Note: Diodes are IN3064 or equivalents.
06780J-7
Input timing measurement reference levels Output timing measurement reference levels
Figure 3.
Test Setup
SWITCHING TEST WAVEFORM
3V 1.5 V 0V Input Output Test Points 1.5 V 0.8 V 0.45 V Input Output 2.4 V 2.0 V Test Points 0.8 V 2.0 V
Note: For CL = 30 pF.
Note: For CL = 100 pF.
06780J-8
KEY TO SWITCHING WAVEFORMS
WAVEFORM INPUTS Steady Changing from H to L Changing from L to H Don't Care, Any Change Permitted Does Not Apply Changing, State Unknown Center Line is High Impedance State (High Z) OUTPUTS
KS000010-PAL
AM27C1024
9
AC CHARACTERISTICS
Parameter Symbols JEDEC tAVQV tELQV tGLQV tEHQZ tGHQZ Standard tACC tCE tOE tDF (Note 2) Description Address to Output Delay Chip Enable to Output Delay Test Setup CE#, OE# = VIL OE# = VIL Max Max Max Max -55 55 55 40 30 -70 70 70 40 30 AM27C1024 -90 90 90 45 40 -120 -150 -200 -255 120 120 50 50 150 150 65 50 200 200 75 50 250 250 75 50 Unit ns ns ns ns
Output Enable to Output Delay CE# = VIL Chip Enable High or Output Enable High to Output High Z, Whichever Occurs First Output Hold Time from Addresses, CE# or OE#, Whichever Occurs First
tAXQX
tOH
Min
0
0
0
0
0
0
0
ns
Caution: Do not remove the device from (or insert it into) a socket or board that has VPP or VCC applied.
Notes:
1. VCC must be applied simultaneously or before VPP, and removed simultaneously or after VPP. 2. This parameter is sampled and not 100% tested. 3. Switching characteristics are over operating range, unless otherwise specified. 4. See Figure 3 and Table 1 for test specifications.
SWITCHING WAVEFORMS
2.4 Addresses 0.45 CE# tCE OE# tOE High Z tACC (Note 1) tOH Valid Output High Z
06780J-9
2.0 0.8
Addresses Valid
2.0 0.8
tDF (Note 2)
Output
Notes: 1. OE# may be delayed up to tACC - tOE after the falling edge of the addresses without impact on tACC. 2. tDF is specified from OE# or CE#, whichever occurs first.
PACKAGE CAPACITANCE
Parameter Description Input Capacitance Output Capacitance CDV040 Test Conditions VIN = 0 VOUT = 0 Typ 9 12 Max 12 14 PD 040 Typ 7 11 Max 12 14 PL 044 Typ 8 11 Max 10 14 Unit pF pF
Parameter Symbol CIN COUT
Notes: 1. This parameter is only sampled and not 100% tested. 2. TA = +25C, f = 1 MHz.
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AM27C1024
PHYSICAL DIMENSIONS* CDV040--40-Pin Ceramic Dual In-Line Package, UV Lens (measured in inches)
DATUM D CENTER PLANE
1
UV Lens .565 .605
INDEX AND TERMINAL NO. 1 I.D. AREA
TOP VIEW DATUM D CENTER PLANE 2.035 2.080 BASE PLANE SEATING PLANE .160 .220 .015 .060 .125 .200 .300 BSC .045 .065 .014 .026 .600 BSC .100 BSC .008 .018 .700 MAX
94 105
.005 MIN
SIDE VIEW
END VIEW
16-000038H-3 CDV040 DF11 3-30-95 ae
* For reference only. BSC is an ANSI standard for Basic Space Centering.
PD 040--40-Pin Plastic Dual In-Line Package (measured in inches)
2.040 2.080 40 21 .530 .580 20 .045 .065 .140 .225 .005 MIN 0 10 .630 .700 .008 .015 .600 .625
Pin 1 I.D.
SEATING PLANE .120 .160 .090 .110 .014 .022 .015 .060
16-038-SC_AF PD 040 DG76 2-28-95 ae
AM27C1024
11
PHYSICAL DIMENSIONS PL 044--44-Pin Plastic Leaded Chip Carrier (measured in inches)
.685 .695 .042 .056 .062 .083
.650 .656
Pin 1 I.D. .685 .695 .650 .656 .500 .590 REF .630
.013 .021
.026 .032
.050 REF
.009 .015
.090 .120 .165 .180
SEATING PLANE
TOP VIEW
SIDE VIEW
16-038-SQ PL 044 EC80 11.3.97 lv
l
REVISION SUMMARY FOR AM27C1024 Revision J
Global Changed formatting to match current data sheets. Distinctive Characteristics
Low power consumption: Changed 100 A to 20 A.
Trademarks Copyright (c) 1998 Advanced Micro Devices, Inc. All rights reserved. AMD, the AMD logo, and combinations thereof are trademarks of Advanced Micro Devices, Inc. Flashrite is a trademark of Advanced Micro Devices, Inc. Product names used in this publication are for identification purposes only and may be trademarks of their respective companies.
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AM27C1024

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